1. Field of the Invention
The present invention relates to a method of fabricating a microelectronic device, and more particularly, to a method of fabricating dual damascene interconnections for use in or with a microelectronic device.
2. Description of the Related Art
As microelectronic devices have become more efficient and highly integrated, multi-layered interconnections are more widely used in fabricating such devices. To obtain a reliable device including multi-layered interconnections, each interconnection layer is preferably formed in a planar fashion. To achieve such a planar configuration, dual damascene interconnections have become a familiar fabrication technique.
Among methods of fabricating dual damascene interconnections that have lately attracted considerable attention, one widely used technique is to fill a via with a filler made of such materials as spin-on-glass (SOG), spin-on-polymer (SOP), SOG with a dye, SOP with a dye, or the like. When the via is not filled with a filler, the via may create a step height at a photoresist layer coated for forming a trench, resulting in a reduction in the depth of focus (DOF) margin; also, an etch stop layer may be etched during etching and cleaning steps thereby exposing a lower interconnection, and possibly degrading electrical properties of the lower interconnection.
However, when a via is filled with a conventional filler 20, as shown for example in FIG. 1, a base material, such as nitrogen or amine, remaining in an interlayer dielectric (to be abbreviated as “ILD” hereinbelow) 18, which may result from an ashing process performed for removing a photoresist pattern for patterning a via 19 using nitrogen-based plasma, is easily diffused along the filler 20, as indicated by an arrow labeled 27, exhibiting outgassing. Such diffused base material will tend to neutralize acids (H+) generated in an exposure portion 22b of a photoresist layer 22 exposed by exposure light 26 which has been transmitted through a transmission region 25 of a mask 24 used in forming a trench. As a result, an exposure portion 22b of photoresist layer 22 and upper regions around the via 19 may not be properly dissolved in a developer, resulting in photoresist poisoning, that is, a photoresist pattern is not properly formed. In FIG. 1, reference numeral 10 denotes a substrate, 12 a lower ILD, 14 a lower interconnection, and 16 an etch stop layer, respectively.
FIG. 2 is a scanning electron microscope (SEM) image illustrating the product of a conventional method of fabricating conventional dual damascene interconnections using methyl silsesquioxane (MSQ) with a dye as a via filling material. As shown in FIG. 2, a photoresist pattern having a poor profile is formed on the via 19 or no photoresist pattern is formed at all. Accordingly, improvement in the techniques of fabricating dual damascene interconnections in a reliable manner is highly required.